In previous technology generations, integrated circuits (or chipsets) were powered using 5V and could easily withstand voltages up to several volts higher. In order to protect such a chipset against transient high voltage spikes, such as those caused by lightening, known avalanche (or low capacitance steering diodes forming a bridge around such a diode) or Zener diodes have been employed to limit the voltage experienced by the chipset. The typical breakdown or turn-on voltage for transient voltage suppression devices such as the aforementioned Zener or avalanche diodes is in the range of about 5V-8V, making such devices ideal for a chipset driven by a 5V power supply. In a typical transient voltage suppression device, such as a Zener diode, the device breaks down at a fixed and known reverse bias, typically in a reversible manner, such that large current can be born by the diode. Because of the relatively low impedance in the breakdown state, the voltage across the diode “clamps” at a voltage approximately the same as the breakdown voltage, that is, the voltage does not rise substantially, even in the presence of high voltage spikes. A transient voltage suppression device that is integrated into a chipset is thus able to maintain the voltage that the chipset experiences to a value characteristic of the breakdown voltage of the particular transient suppression device.
Although such transient suppression devices may provide adequate protection for chipsets based on 5V power supply technology, as electronic devices scale to smaller dimensions, a concomitant reduction in power supply voltage is useful to fully realize performance benefits afforded by the smaller device dimensions. In turn, the smaller device geometries render electronic components, such as transistors, much more sensitive to voltage, in part because of the higher fields generated at the smaller dimensions. Many present-day chipsets operate at 3.3V, 2.5V, or as low as 1.8V.
This very pronounced decrease in the maximum operating voltage of current day electronics has therefore created a need for an improved Zener/avalanche diode. Thus, a standard 6-8V Zener diode clamps at a much higher voltage level than a chipset designed for 1.8V, 2.5V, or 3.3V operation can withstand, making the standard Zener diode an ineffective protection device. Such a device may still provide some protection for a very short duration (e.g., 100 ns) event such as electrostatic discharge (ESD), but not for longer duration (i.e. >30 μs) events including lightning-induced surges.
Several types of devices have been developed to provide clamping at lower voltages. These include a punch-through vertical NPN transistor that is designed to conduct at relatively low voltage levels by virtue of a very narrow base region. In addition, a 4-layer vertical NPN transistor that is described in U.S. Pat. No. 5,880,511 and U.S. RE 38,608 E. Conventional silicon controlled rectifiers (SCR) may also be used to provide low voltage clamping.
FIG. 1a depicts a schematic of a known vertical NPN transistor 100. In operation, a punch-through vertical NPN transistor, such as transistor 100, has a “programmed” breakdown voltage that is set by the transistor base width. The punch through voltage may be defined as the voltage at which the space charge region of the collector base junction merges with the emitter. At present, the lowest turn-on voltage for such devices is about 2.5V, and the snapback voltage is typically not below 2.0V, in part to limits placed by current device processing technology. Furthermore, the base width in such vertical NPN devices must be designed to be a minimum thickness in order to avoid premature turn-on or leakage at temperature extremes, which adds extra resistance (and thus higher clamping voltage) during a high voltage transient.
FIG. 1b depicts a schematic of a 4-layer device structure 120, as described in U.S. Pat. No. 5,880,511. This structure is achieved using a processing sequence that adds an extra, lightly doped p-type layer in the base, which creates a more effective punch-through transistor, thereby helping to lower the clamping voltage. Additionally, the four layer device 120 has lower leakage currents at voltages just below the turn-on voltage. However, the four layer device also does not provide a breakdown voltage below about 2.5V, with a minimal voltage snapback (i.e. 2V minimum), similar to the NPN vertical punch-through device.
FIG. 1c illustrates a schematic of a known SCR device structure 140 that includes a PNP transistor 150 and NPN transistor 160. In typical implementation, the SCR comprises a four layer P-N-P-N stack. As illustrated, the base of the PNP transistor 150 is shared in common with the emitter of the NPN transistor and the collector of the PNP transistor is in common with the base of the NPN transistor. A gate terminal is connected to the base of the NPN transistor.
At present, SCR devices exist that, when triggered, can clamp to voltages on the order of 1-1.5V, depending upon device size. However, once triggered, an SCR remains in a conducting state until the “holding current” is removed. This value may vary with design and processing parameters, but typically an SCR may remain turned on after an over-voltage event has passed, and thus may interfere in normal operation of the devices and circuits that the SCR is designed to protect. For this reason, SCRs are generally considered to be a non-ideal solution for use as circuit protection devices.
In view of the above, it is apparent that a need exists for transient voltage suppression devices that provide improved protection for devices operating at low power supply voltages.